1. Technical Field
The present invention generally relates to design structures, and more specifically, design structures for computer memory systems and in particular to accessing data in computer memory systems. Still more particularly, the present invention relates to scheduling access to memory data within computer memory systems.
2. Description of the Related Art
In a data processing system, requests for data stored within memory (memory data) are received by a memory controller, which controls access to the memory data. In a Fully Buffered Dual Inline Memory Module (FBDIMM) memory subsystem, when a particular data item is requested through the memory controller, a command packet is sent (via serial signaling) down a chain of buffer modules until the packet reaches a buffer chip that is connected to the Dynamic Random Access Memory (DRAM) chips containing the requested data.
The buffer modules are often interconnected via a parallel Double Data Rate (DDR)-based interface. The buffer chip uses the DRAM protocol to access the data. The buffer is referred to as an AMB (advanced memory buffer). The AMB is designed to only take action in response to memory controller commands. The AMB delivers DRAM commands from the memory controller over the FBDIMM interface without any alteration to the DRAM devices over the parallel DDR-based interface.
DRAM chips are very high volume parts with many speed grades available at various costs. The time delay (i.e., the latency) at the memory controller to receive the data from the DRAM chips depends on the speed rating/grade of the parts. Also, another component of the time delay seen by the memory controller is the time taken for the command packet to reach the destination buffer chip and for that buffer chip to send the requested data once the buffer chip has obtained the data from the DRAM chips.
With FBDIMM technology, the signaling interface between the memory controller and the DRAM chips is split into two independent signaling interfaces, with a buffer between the two interfaces. The first interface between the buffer and DRAM chips supports DDR2 (DDR2 is the second (2) generation DDR interface standard, where DDR is a type of synchronous dynamic random access memory (SDRAM) memory access). However, the second interface between the memory controller and the buffer is a point-to-point serial interface.
Double-Data-Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) achieves greater bandwidth than the preceding technology, single-data-rate (SDR) SDRAM, by transferring data on both the rising and falling edges of the clock signal. The greater bandwidth nearly doubles the transfer rate, without increasing the frequency of the front side bus. Thus a 100 MHz DDR system has an effective clock rate of 200 MHz when compared to equivalent SDR SDRAM. With data being transferred 8 bytes at a time, DDR RAM gives a transfer rate of (memory bus clock rate)×2 (for dual rate)×8 (number of bytes transferred). Thus with a bus frequency of 100 MHz, DDR-SDRAM gives a maximum transfer rate of 1600 Megabytes per second (MB/s) (i.e., DDR 1600 speeds).
Since the FBDIMM interface is based on serial differential signaling (similar to Serial Advanced Technology Attachment (ATA), Serial Small Computer System Interface (SCSI), Peripheral Computer Interconnect (PCI) Express, and others), a memory controller is capable of supporting multiple generations of FBDIMM technology-based components. FBDIMM technology, which is a new memory architecture, addresses the scaling needs of both capacity and bandwidth and enables memory to keep pace with processor and I/O improvements in enterprise platforms.
In an FBDIMM memory subsystem, there are two possible latency modes, fixed and variable. In the fixed latency mode, the buffer chips hold data when the buffer chips are near to the memory controller. The buffer chips also hold data when the DRAMs to which the buffer chips are attached are faster than the other buffer chips in the chain. The buffer chips hold data in order to make the total delay, as seen by the memory controller, the same for all data. The advantage of using a constant total delay is that the constant total delay greatly simplifies the design of the memory controller. However, the disadvantage is that all memory requests are delayed to match the delay of the slowest or farthest DRAM. Variable latency, in contrast, allows each buffer chip to return data as soon as possible. The benefit is, of course, that every data item is accessed in the minimum possible time. However, the drawback is that since all return data must pass through the same chain of buffer chips, a burden is placed on the memory controller to time the requests in a manner that avoids bus conflicts when returning data from different DRAMs.